Lattice FPGA iCE40 LP/HX 1280 Cells, 64 kB 160 Blocks, 49-Pin UCBGA
- RS-stocknr.:
- 168-4224
- Fabrikantnummer:
- ICE40LP1K-CM49
- Fabrikant:
- Lattice Semiconductor
Momenteel niet beschikbaar
We weten niet of dit item nog op voorraad komt, RS is van plan dit binnenkort uit ons assortiment te halen.
- RS-stocknr.:
- 168-4224
- Fabrikantnummer:
- ICE40LP1K-CM49
- Fabrikant:
- Lattice Semiconductor
Specificaties
Datasheets
Wetgeving en conformiteit
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Lattice Semiconductor | |
| Product Type | FPGA | |
| Series | iCE40 LP/HX | |
| Number of Logic Cells | 1280 | |
| Number of Logic Units | 160 | |
| Number of Registers | 1280 | |
| Mount Type | Surface | |
| Package Type | UCBGA | |
| Minimum Supply Voltage | 1.14V | |
| Maximum Supply Voltage | 1.26V | |
| Pin Count | 49 | |
| Number of I/Os | 206 | |
| Number of RAM Bits | 64kB | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Height | 0.9mm | |
| Standards/Approvals | Halogen Free | |
| Width | 3 mm | |
| Length | 3mm | |
| Automotive Standard | No | |
| Alles selecteren | ||
|---|---|---|
Merk Lattice Semiconductor | ||
Product Type FPGA | ||
Series iCE40 LP/HX | ||
Number of Logic Cells 1280 | ||
Number of Logic Units 160 | ||
Number of Registers 1280 | ||
Mount Type Surface | ||
Package Type UCBGA | ||
Minimum Supply Voltage 1.14V | ||
Maximum Supply Voltage 1.26V | ||
Pin Count 49 | ||
Number of I/Os 206 | ||
Number of RAM Bits 64kB | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Height 0.9mm | ||
Standards/Approvals Halogen Free | ||
Width 3 mm | ||
Length 3mm | ||
Automotive Standard No | ||
- Land van herkomst:
- KR
Field Programmable Gate Arrays, Lattice Semiconductor
An FPGA is a semiconductor device consisting of a Matrix of Configurable Logic Blocks (CLBs) connected through programmable interconnects. The user determines these interconnections by programming SRAM. A CLB can be simple (AND, OR gates, etc) or complex (a Block of RAM). The FPGA allows changes to be MADE to a design even after the device is soldered into a PCB.
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