Lattice FPGA iCE40HX1K-VQ100 iCE40 1280 Cells, 64000 bit 160 Blocks, 100-Pin VQFP
- RS-stocknr.:
- 772-0045
- Fabrikantnummer:
- iCE40HX1K-VQ100
- Fabrikant:
- Lattice Semiconductor
Bulkkorting beschikbaar
Subtotaal (1 eenheid)*
€ 6,44
(excl. BTW)
€ 7,79
(incl. BTW)
GRATIS bezorging voor bestellingen vanaf € 75,00
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Aantal stuks | Per stuk |
|---|---|
| 1 - 9 | € 6,44 |
| 10 - 49 | € 6,28 |
| 50 - 99 | € 6,11 |
| 100 - 199 | € 5,96 |
| 200 + | € 5,81 |
*prijsindicatie
- RS-stocknr.:
- 772-0045
- Fabrikantnummer:
- iCE40HX1K-VQ100
- Fabrikant:
- Lattice Semiconductor
Specificaties
Datasheets
Wetgeving en conformiteit
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Lattice Semiconductor | |
| Product Type | FPGA | |
| Series | iCE40 | |
| Number of Logic Cells | 1280 | |
| Number of Logic Units | 160 | |
| Number of Registers | 1280 | |
| Mount Type | Surface | |
| Package Type | VQFP | |
| Minimum Supply Voltage | 1.14V | |
| Pin Count | 100 | |
| Maximum Supply Voltage | 1.26V | |
| Number of RAM Bits | 64000bit | |
| Number of I/Os | 72 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Length | 14mm | |
| Width | 14 mm | |
| Standards/Approvals | No | |
| Height | 1.05mm | |
| Automotive Standard | No | |
| Alles selecteren | ||
|---|---|---|
Merk Lattice Semiconductor | ||
Product Type FPGA | ||
Series iCE40 | ||
Number of Logic Cells 1280 | ||
Number of Logic Units 160 | ||
Number of Registers 1280 | ||
Mount Type Surface | ||
Package Type VQFP | ||
Minimum Supply Voltage 1.14V | ||
Pin Count 100 | ||
Maximum Supply Voltage 1.26V | ||
Number of RAM Bits 64000bit | ||
Number of I/Os 72 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Length 14mm | ||
Width 14 mm | ||
Standards/Approvals No | ||
Height 1.05mm | ||
Automotive Standard No | ||
Field Programmable Gate Arrays, Lattice Semiconductor
An FPGA is a semiconductor device consisting of a Matrix of Configurable Logic Blocks (CLBs) connected through programmable interconnects. The user determines these interconnections by programming SRAM. A CLB can be simple (AND, OR gates, etc) or complex (a Block of RAM). The FPGA allows changes to be MADE to a design even after the device is soldered into a PCB.
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