Lattice FPGA iCE40HX4K-TQ144, iCE40 HX 3520 Cells, 80kbit, 440 Blocks, 144-Pin TQFP
- RS-stocknr.:
- 772-0057P
- Fabrikantnummer:
- iCE40HX4K-TQ144
- Fabrikant:
- Lattice Semiconductor
Subtotaal 1 eenheid (geleverd op een tray)*
€ 7,48
(excl. BTW)
€ 9,05
(incl. BTW)
GRATIS bezorging voor bestellingen vanaf € 75,00
Op voorraad
- 455 stuk(s) klaar voor verzending vanaf een andere locatie
Heeft u meer nodig? Klik op 'Controleer leverdata' voor extra voorraad en levertijden.
Aantal stuks | Per stuk |
|---|---|
| 1 + | € 7,48 |
*prijsindicatie
- RS-stocknr.:
- 772-0057P
- Fabrikantnummer:
- iCE40HX4K-TQ144
- Fabrikant:
- Lattice Semiconductor
Specificaties
Datasheets
Wetgeving en conformiteit
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Lattice Semiconductor | |
| Family Name | iCE40 HX | |
| Number of Logic Cells | 3520 | |
| Number of Logic Units | 440 | |
| Number of Registers | 3520 | |
| Mounting Type | Surface Mount | |
| Package Type | TQFP | |
| Pin Count | 144 | |
| Number of RAM Bits | 80kbit | |
| Dimensions | 20 x 20 x 1.45mm | |
| Height | 1.45mm | |
| Length | 20mm | |
| Minimum Operating Supply Voltage | 1.14 V | |
| Width | 20mm | |
| Maximum Operating Temperature | +85 °C | |
| Minimum Operating Temperature | -40 °C | |
| Maximum Operating Supply Voltage | 1.26 V | |
| Alles selecteren | ||
|---|---|---|
Merk Lattice Semiconductor | ||
Family Name iCE40 HX | ||
Number of Logic Cells 3520 | ||
Number of Logic Units 440 | ||
Number of Registers 3520 | ||
Mounting Type Surface Mount | ||
Package Type TQFP | ||
Pin Count 144 | ||
Number of RAM Bits 80kbit | ||
Dimensions 20 x 20 x 1.45mm | ||
Height 1.45mm | ||
Length 20mm | ||
Minimum Operating Supply Voltage 1.14 V | ||
Width 20mm | ||
Maximum Operating Temperature +85 °C | ||
Minimum Operating Temperature -40 °C | ||
Maximum Operating Supply Voltage 1.26 V | ||
Field Programmable Gate Arrays, Lattice Semiconductor
An FPGA is a semiconductor device consisting of a matrix of Configurable Logic Blocks (CLBs) connected through programmable interconnects. The user determines these interconnections by programming SRAM. A CLB can be simple (AND, OR gates, etc) or complex (a block of RAM). The FPGA allows changes to be made to a design even after the device is soldered into a PCB.