Renesas Electronics 8305AGLF Clock Buffer, 16-Pin 4 TSSOP
- RS-stocknr.:
- 216-6206
- Fabrikantnummer:
- 8305AGLF
- Fabrikant:
- Renesas Electronics
Subtotaal (1 verpakking van 2 eenheden)*
€ 6,73
(excl. BTW)
€ 8,144
(incl. BTW)
GRATIS bezorging voor bestellingen vanaf € 75,00
Laatste voorraad RS
- Laatste 148 stuk(s), klaar voor verzending vanaf een andere locatie
Aantal stuks | Per stuk | Per verpakking* |
|---|---|---|
| 2 + | € 3,365 | € 6,73 |
*prijsindicatie
- RS-stocknr.:
- 216-6206
- Fabrikantnummer:
- 8305AGLF
- Fabrikant:
- Renesas Electronics
Specificaties
Datasheets
Wetgeving en conformiteit
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Mount Type | Surface | |
| Package Type | TSSOP | |
| Pin Count | 16 | |
| Minimum Supply Voltage | 1.5V | |
| Maximum Supply Voltage | 3.3V | |
| Minimum Operating Temperature | 0°C | |
| Maximum Operating Temperature | 70°C | |
| Height | 0.9mm | |
| Length | 4mm | |
| Width | 3.3 mm | |
| Series | 8305A | |
| Standards/Approvals | No | |
| Number of Outputs | 4 | |
| Automotive Standard | No | |
| Alles selecteren | ||
|---|---|---|
Merk Renesas Electronics | ||
Product Type Clock Buffer | ||
Mount Type Surface | ||
Package Type TSSOP | ||
Pin Count 16 | ||
Minimum Supply Voltage 1.5V | ||
Maximum Supply Voltage 3.3V | ||
Minimum Operating Temperature 0°C | ||
Maximum Operating Temperature 70°C | ||
Height 0.9mm | ||
Length 4mm | ||
Width 3.3 mm | ||
Series 8305A | ||
Standards/Approvals No | ||
Number of Outputs 4 | ||
Automotive Standard No | ||
The Renesas Electronics ICS8305 is a low skew, 1-to-4, Differential/ LVCMOS-to-LVCMOS/LVTTL Fanout Buffer. The ICS8305 has selectable clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A separate output enable pin controls whether the outputs are in the active or high impedance state.
Four LVCMOS / LVTTL outputs, 7 output impedance
Selectable differential or LVCMOS / LVTTL clock inputs
CLK, nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
LVCMOS_CLK supports the following input types: LVCMOS,
LVTTL
Maximum output frequency: 350MHz
Output skew: 35ps (maximum)
Part-to-part skew: 700ps (maximum)
Additive phase jitter, RMS: 0.04ps (typical)
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