Renesas Electronics 8305AGILF Clock Buffer, 16-Pin 4 TSSOP
- RS-stocknr.:
- 216-6204
- Fabrikantnummer:
- 8305AGILF
- Fabrikant:
- Renesas Electronics
Bulkkorting beschikbaar
Subtotaal (1 verpakking van 2 eenheden)*
€ 7,15
(excl. BTW)
€ 8,652
(incl. BTW)
Voeg 24 eenheden toe voor gratis bezorging
Laatste voorraad RS
- Laatste 68 stuk(s), klaar voor verzending vanaf een andere locatie
Aantal stuks | Per stuk | Per verpakking* |
|---|---|---|
| 2 - 8 | € 3,575 | € 7,15 |
| 10 - 18 | € 3,48 | € 6,96 |
| 20 - 48 | € 3,39 | € 6,78 |
| 50 - 98 | € 3,30 | € 6,60 |
| 100 + | € 3,22 | € 6,44 |
*prijsindicatie
- RS-stocknr.:
- 216-6204
- Fabrikantnummer:
- 8305AGILF
- Fabrikant:
- Renesas Electronics
Specificaties
Datasheets
Wetgeving en conformiteit
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Mount Type | Surface | |
| Package Type | TSSOP | |
| Minimum Supply Voltage | 1.8V | |
| Pin Count | 16 | |
| Maximum Supply Voltage | 3.3V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Width | 6.4 mm | |
| Standards/Approvals | No | |
| Length | 4.9mm | |
| Series | 8305A | |
| Height | 1.2mm | |
| Number of Outputs | 4 | |
| Automotive Standard | No | |
| Alles selecteren | ||
|---|---|---|
Merk Renesas Electronics | ||
Product Type Clock Buffer | ||
Mount Type Surface | ||
Package Type TSSOP | ||
Minimum Supply Voltage 1.8V | ||
Pin Count 16 | ||
Maximum Supply Voltage 3.3V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Width 6.4 mm | ||
Standards/Approvals No | ||
Length 4.9mm | ||
Series 8305A | ||
Height 1.2mm | ||
Number of Outputs 4 | ||
Automotive Standard No | ||
The Renesas Electronics ICS8305I is a low skew, 1-to-4, Differential/LVCMOS-toLVCMOS/LVTTL Fanout Buffer. The ICS8305I has selectable clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A separate output enable pin controls whether the outputs are in the active or high impedance state.
4 LVCMOS/LVTTL outputs
Selectable differential or LVCMOS/LVTTL clock inputs
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
LVCMOS_CLK supports the following input types:
LVCMOS, LVTTL
Maximum output frequency: 350MHz
Output skew: 40ps (maximum)
Part-to-part skew: 700ps (maximum)
Additive phase jitter, RMS: 0.04ps (typical)
3.3V core, 3.3V, 2.5V or 1.8V output operating supply
-40°C to 85°C ambient operating temperature
Lead-Free package fully RoHS compliant
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