Renesas Electronics 2305A-1DCG Clock Buffer 8-Pin SOIC
- RS-stocknr.:
- 263-7871
- Fabrikantnummer:
- 2305A-1DCG
- Fabrikant:
- Renesas Electronics
Bulkkorting beschikbaar
Subtotaal (1 verpakking van 5 eenheden)*
€ 4,78
(excl. BTW)
€ 5,785
(incl. BTW)
Voeg 100 eenheden toe voor gratis bezorging
Tijdelijk niet op voorraad
- Verzending vanaf 22 mei 2026
Heeft u meer nodig? Klik op 'Controleer leverdata' voor extra voorraad en levertijden.
Aantal stuks | Per stuk | Per verpakking* |
|---|---|---|
| 5 - 5 | € 0,956 | € 4,78 |
| 10 - 20 | € 0,856 | € 4,28 |
| 25 - 45 | € 0,816 | € 4,08 |
| 50 - 90 | € 0,796 | € 3,98 |
| 95 + | € 0,78 | € 3,90 |
*prijsindicatie
- RS-stocknr.:
- 263-7871
- Fabrikantnummer:
- 2305A-1DCG
- Fabrikant:
- Renesas Electronics
Specificaties
Datasheets
Wetgeving en conformiteit
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Maximum Input Frequency | 133MHz | |
| Mount Type | Surface | |
| Package Type | SOIC | |
| Pin Count | 8 | |
| Number of Outputs | 8 | |
| Minimum Supply Voltage | -0.5V | |
| Maximum Supply Voltage | 4.6V | |
| Minimum Operating Temperature | 0°C | |
| Maximum Operating Temperature | 70°C | |
| Height | 1.5mm | |
| Length | 4.9mm | |
| Width | 3.9 mm | |
| Standards/Approvals | RoHS | |
| Series | IDT2305A | |
| Automotive Standard | No | |
| Alles selecteren | ||
|---|---|---|
Merk Renesas Electronics | ||
Product Type Clock Buffer | ||
Maximum Input Frequency 133MHz | ||
Mount Type Surface | ||
Package Type SOIC | ||
Pin Count 8 | ||
Number of Outputs 8 | ||
Minimum Supply Voltage -0.5V | ||
Maximum Supply Voltage 4.6V | ||
Minimum Operating Temperature 0°C | ||
Maximum Operating Temperature 70°C | ||
Height 1.5mm | ||
Length 4.9mm | ||
Width 3.9 mm | ||
Standards/Approvals RoHS | ||
Series IDT2305A | ||
Automotive Standard No | ||
- Land van herkomst:
- PH
The Renesas Electronics high-speed phase-lock loop clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. It is an 8-pin version of the accepts one reference input, and drives out five low skew clocks.
Phase lock loop clock distribution
Distributes one clock input to one bank of five outputs
No external RC network required
Power down mode
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