Renesas Electronics 23S05E-1DCG Clock Buffer 8-Pin SOIC
- RS-stocknr.:
- 263-7885
- Fabrikantnummer:
- 23S05E-1DCG
- Fabrikant:
- Renesas Electronics
Bulkkorting beschikbaar
Subtotaal (1 verpakking van 5 eenheden)*
€ 3,79
(excl. BTW)
€ 4,585
(incl. BTW)
GRATIS bezorging voor bestellingen vanaf € 75,00
Tijdelijk niet op voorraad
- Verzending vanaf 22 mei 2026
Heeft u meer nodig? Klik op 'Controleer leverdata' voor extra voorraad en levertijden.
Aantal stuks | Per stuk | Per verpakking* |
|---|---|---|
| 5 - 5 | € 0,758 | € 3,79 |
| 10 - 20 | € 0,686 | € 3,43 |
| 25 - 45 | € 0,65 | € 3,25 |
| 50 - 90 | € 0,636 | € 3,18 |
| 95 + | € 0,624 | € 3,12 |
*prijsindicatie
- RS-stocknr.:
- 263-7885
- Fabrikantnummer:
- 23S05E-1DCG
- Fabrikant:
- Renesas Electronics
Specificaties
Datasheets
Wetgeving en conformiteit
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Maximum Input Frequency | 200MHz | |
| Maximum Propagation Delay Time | 350ps | |
| Mount Type | Surface | |
| Package Type | SOIC | |
| Pin Count | 8 | |
| Number of Outputs | 5 | |
| Minimum Supply Voltage | 3V | |
| Maximum Supply Voltage | 4.6V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Standards/Approvals | No | |
| Series | IDT23S05E | |
| Automotive Standard | No | |
| Alles selecteren | ||
|---|---|---|
Merk Renesas Electronics | ||
Product Type Clock Buffer | ||
Maximum Input Frequency 200MHz | ||
Maximum Propagation Delay Time 350ps | ||
Mount Type Surface | ||
Package Type SOIC | ||
Pin Count 8 | ||
Number of Outputs 5 | ||
Minimum Supply Voltage 3V | ||
Maximum Supply Voltage 4.6V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Standards/Approvals No | ||
Series IDT23S05E | ||
Automotive Standard No | ||
- Land van herkomst:
- PH
The Renesas Electronics zero delay clock buffer is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 200MHz. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, it enters power down.
Distributes one clock input to one bank of five outputs
Zero input-output delay
Output skew < 250ps
Low jitter <200 ps cycle-to-cycle
No external RC network required
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