Infineon S27KL0642DPBHI020 SDRAM 64 MB Surface, 24-Pin 8 bit FBGA-24 Ball
- RS-stocknr.:
- 273-7512
- Fabrikantnummer:
- S27KL0642DPBHI020
- Fabrikant:
- Infineon
Bulkkorting beschikbaar
Subtotaal (1 tray van 338 eenheden)*
€ 924,768
(excl. BTW)
€ 1.119,118
(incl. BTW)
GRATIS bezorging voor bestellingen vanaf € 90,00
Tijdelijk niet op voorraad
- Verzending vanaf 27 november 2026
Heeft u meer nodig? Klik op 'Controleer leverdata' voor extra voorraad en levertijden.
Aantal stuks | Per stuk | Per tray* |
|---|---|---|
| 338 - 676 | € 2,736 | € 924,77 |
| 1014 + | € 2,629 | € 888,60 |
*prijsindicatie
- RS-stocknr.:
- 273-7512
- Fabrikantnummer:
- S27KL0642DPBHI020
- Fabrikant:
- Infineon
Specificaties
Datasheets
Wetgeving en conformiteit
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Infineon | |
| Product Type | SDRAM | |
| Memory Size | 64MB | |
| Data Bus Width | 8bit | |
| Maximum Clock Frequency | 200MHz | |
| Number of Bits per Word | 16 | |
| Mount Type | Surface | |
| Package Type | FBGA-24 Ball | |
| Minimum Operating Temperature | -40°C | |
| Pin Count | 24 | |
| Maximum Operating Temperature | 105°C | |
| Standards/Approvals | No | |
| Height | 1mm | |
| Length | 6mm | |
| Series | S27K | |
| Minimum Supply Voltage | 1.8V | |
| Automotive Standard | AEC-Q100 Grade 2 & 3 | |
| Maximum Supply Voltage | 3.6V | |
| Supply Current | 360μA | |
| Alles selecteren | ||
|---|---|---|
Merk Infineon | ||
Product Type SDRAM | ||
Memory Size 64MB | ||
Data Bus Width 8bit | ||
Maximum Clock Frequency 200MHz | ||
Number of Bits per Word 16 | ||
Mount Type Surface | ||
Package Type FBGA-24 Ball | ||
Minimum Operating Temperature -40°C | ||
Pin Count 24 | ||
Maximum Operating Temperature 105°C | ||
Standards/Approvals No | ||
Height 1mm | ||
Length 6mm | ||
Series S27K | ||
Minimum Supply Voltage 1.8V | ||
Automotive Standard AEC-Q100 Grade 2 & 3 | ||
Maximum Supply Voltage 3.6V | ||
Supply Current 360μA | ||
The Infineon DRAM is a high speed CMOS, self refresh DRAM, with HYPERBUS interface. The DRAM array uses dynamic cells that require periodic refresh. Refresh control logic within the device manages the refresh operations on the DRAM array when the memory is not being actively read or written by the HYPERBUS interface master. Since the host is not required to manage any refresh operations, the DRAM array appears to the host as though the memory uses static cells that retain data without refresh. Hence, the memory is more accurately described as Pseudo Static RAM.
200 MHz maximum clock rate
Data throughput up to 400 MBps
Bidirectional read write data strobe
Automotive AEC Q100 Grade 2 and 3
Optional DDR centre aligned read strobe
DDR transfers data on both edges of the clock
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