Winbond W972GG6KB25I SDRAM 2 GB Surface, 84-Pin 16 bit WBGA

Name: Winbond W972GG6KB25I SDRAM 2 GB Surface, 84-Pin 16 bit WBGA
Brand: Winbond
SKU: 188-2835
Availability: OutOfStock

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Specificaties

Datasheets

Wetgeving en conformiteit

Productomschrijving

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Alles selecteren	Attribuut	Waarde
	Merk	Winbond
	Product Type	SDRAM
	Memory Size	2 GB
	Mount Type	Surface
	Pin Count	84
	Data Bus Width	16 bit
	Package Type	WBGA
	Address Bus Width	17 bit
	Automotive Standard	No
	Height	600 μm
	Length	12.6 mm
	Maximum Clock Frequency	533 MHz
	Maximum Operating Temperature	95 °C
	Maximum Random Access Time	0.4 ns
	Maximum Supply Voltage	1.9 V
	Minimum Operating Temperature	-40 °C
	Minimum Supply Voltage	1.7 V
	Number of Bits per Word	8
	Number of Words	256M
	Organisation	256M x 8 bit
	Series	W972GG6KB
	Standards/Approvals	RoHS
	Supply Current	280 mA
	Width	8.1 mm

	Alles selecteren
	Merk Winbond
	Product Type SDRAM
	Memory Size 2 GB
	Mount Type Surface
	Pin Count 84
	Data Bus Width 16 bit
	Package Type WBGA
	Address Bus Width 17 bit
	Automotive Standard No
	Height 600 μm
	Length 12.6 mm
	Maximum Clock Frequency 533 MHz
	Maximum Operating Temperature 95 °C
	Maximum Random Access Time 0.4 ns
	Maximum Supply Voltage 1.9 V
	Minimum Operating Temperature -40 °C
	Minimum Supply Voltage 1.7 V
	Number of Bits per Word 8
	Number of Words 256M
	Organisation 256M x 8 bit
	Series W972GG6KB
	Standards/Approvals RoHS
	Supply Current 280 mA
	Width 8.1 mm

The W972GG6KB is a 2G bits DDR2 SDRAM, and speed involving -18, -25/25I, and -3/-3I.

Double Data Rate architecture: two data transfers per clock cycle

CAS Latency: 3, 4, 5, 6 and 7

Burst Length: 4 and 8

Bi-directional, differential data strobes (DQS and /DQS ) are transmitted / received with data

Edge-aligned with Read data and center-aligned with Write data

DLL aligns DQ and DQS transitions with clock

Differential clock inputs (CLK and /CLK)

Data masks (DM) for write data

Commands entered on each positive CLK edge, data and data mask are referenced to both edges of /DQS

Posted /CAS programmable additive latency supported to make command and data bus efficiency

Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)

Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality

Auto-precharge operation for read and write bursts

Auto Refresh and Self Refresh modes

Precharged Power Down and Active Power Down

Write Data Mask

Write Latency = Read Latency - 1 (WL = RL - 1)

Interface: SSTL_18

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