Intelligent Memory IME1G08D2DEBG-25I SDRAM 1 GB Surface, 60-Pin 16 bit FBGA-60 Ball
- RS-stocknr.:
- 588-633
- Fabrikantnummer:
- IME1G08D2DEBG-25I
- Fabrikant:
- Intelligent Memory
Subtotaal (1 eenheid)*
€ 6,28
(excl. BTW)
€ 7,60
(incl. BTW)
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Aantal stuks | Per stuk |
|---|---|
| 1 + | € 6,28 |
*prijsindicatie
- RS-stocknr.:
- 588-633
- Fabrikantnummer:
- IME1G08D2DEBG-25I
- Fabrikant:
- Intelligent Memory
Specificaties
Datasheets
Wetgeving en conformiteit
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Intelligent Memory | |
| Product Type | SDRAM | |
| Memory Size | 1GB | |
| Organisation | 128M x 8 | |
| Data Bus Width | 16bit | |
| Maximum Clock Frequency | 533MHz | |
| Number of Bits per Word | 72 | |
| Maximum Random Access Time | 2.5ns | |
| Number of Words | 16777216 | |
| Mount Type | Surface | |
| Package Type | FBGA-60 Ball | |
| Pin Count | 60 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 95°C | |
| Series | IME1G(08/16)D2DEB | |
| Standards/Approvals | JEDEC, RoHS | |
| Automotive Standard | AEC-Q100 | |
| Maximum Supply Voltage | 1.9V | |
| Minimum Supply Voltage | 1.7V | |
| Alles selecteren | ||
|---|---|---|
Merk Intelligent Memory | ||
Product Type SDRAM | ||
Memory Size 1GB | ||
Organisation 128M x 8 | ||
Data Bus Width 16bit | ||
Maximum Clock Frequency 533MHz | ||
Number of Bits per Word 72 | ||
Maximum Random Access Time 2.5ns | ||
Number of Words 16777216 | ||
Mount Type Surface | ||
Package Type FBGA-60 Ball | ||
Pin Count 60 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 95°C | ||
Series IME1G(08/16)D2DEB | ||
Standards/Approvals JEDEC, RoHS | ||
Automotive Standard AEC-Q100 | ||
Maximum Supply Voltage 1.9V | ||
Minimum Supply Voltage 1.7V | ||
- Land van herkomst:
- TW
The Intelligent Memory Eight bank DDR DRAM is organized as 8 banks x 16Mbit x 8 or 8 banks x 8Mbit x 16. It achieves high-speed data transfer rates by using a chip architecture that prefetches multiple bits and synchronizes the output data with the system clock.
Automatic and controlled precharge command
Power down mode
Auto refresh and self refresh
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