8SLVP1208ANBGI, Clock Buffer LVPECL, 4-Input, 28-Pin LFCSP
- RS-stocknr.:
- 216-6233P
- Fabrikantnummer:
- 8SLVP1208ANBGI
- Fabrikant:
- Renesas Electronics
Bulkkorting beschikbaar
Subtotaal 10 eenheden (geleverd op een tray)*
€ 72,00
(excl. BTW)
€ 87,10
(incl. BTW)
GRATIS bezorging voor bestellingen vanaf € 75,00
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- Plus verzending 397 stuk(s) vanaf 22 december 2025
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|---|---|
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*prijsindicatie
- RS-stocknr.:
- 216-6233P
- Fabrikantnummer:
- 8SLVP1208ANBGI
- Fabrikant:
- Renesas Electronics
Specificaties
Datasheets
Wetgeving en conformiteit
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Renesas Electronics | |
| Logic Family | LVPECL | |
| Logic Function | Clock Buffer | |
| Input Signal Type | LVPECL | |
| Number of Clock Inputs | 4 | |
| Package Type | LFCSP | |
| Pin Count | 28 | |
| Alles selecteren | ||
|---|---|---|
Merk Renesas Electronics | ||
Logic Family LVPECL | ||
Logic Function Clock Buffer | ||
Input Signal Type LVPECL | ||
Number of Clock Inputs 4 | ||
Package Type LFCSP | ||
Pin Count 28 | ||
The Renesas Electronics 8SLVP1208 is a high-performance differential LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVP1208 is characterized to operate from a 3.3V and 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP1208 ideal for those clock distribution applications demanding well-defined performance and repeatability.
Eight low skew, low additive jitter LVPECL output pairs
Two selectable, differential clock input pairs
Differential pairs can accept the following differential input
levels: LVDS, LVPECL, CML
Maximum input clock frequency: 2GHz
LVCMOS interface levels for the control input (input select)
Output skew: 28ps (typical)
Propagation delay: 410ps (maximum)
Low additive phase jitter, RMS: 54.1fs (maximum)
(fREF = 156.25MHz, VPP = 1V, 12kHz - 20MHz)
Two selectable, differential clock input pairs
Differential pairs can accept the following differential input
levels: LVDS, LVPECL, CML
Maximum input clock frequency: 2GHz
LVCMOS interface levels for the control input (input select)
Output skew: 28ps (typical)
Propagation delay: 410ps (maximum)
Low additive phase jitter, RMS: 54.1fs (maximum)
(fREF = 156.25MHz, VPP = 1V, 12kHz - 20MHz)
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