853S011BGILF, Clock Buffer, 2-Input, 8-Pin SOIC
- RS-stocknr.:
- 216-6211
- Fabrikantnummer:
- 853S011BGILF
- Fabrikant:
- Renesas Electronics
Subtotaal (1 tube van 96 eenheden)*
€ 304,896
(excl. BTW)
€ 368,928
(incl. BTW)
GRATIS bezorging voor bestellingen vanaf € 75,00
Op voorraad
- Plus verzending 96 stuk(s) vanaf 22 december 2025
Heeft u meer nodig? Klik op 'Controleer leverdata' voor extra voorraad en levertijden.
Aantal stuks | Per stuk | Per tube* |
|---|---|---|
| 96 + | € 3,176 | € 304,90 |
*prijsindicatie
- RS-stocknr.:
- 216-6211
- Fabrikantnummer:
- 853S011BGILF
- Fabrikant:
- Renesas Electronics
Specificaties
Datasheets
Wetgeving en conformiteit
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Renesas Electronics | |
| Logic Function | Clock Buffer | |
| Input Signal Type | LVPECL | |
| Number of Clock Inputs | 2 | |
| Package Type | SOIC | |
| Pin Count | 8 | |
| Alles selecteren | ||
|---|---|---|
Merk Renesas Electronics | ||
Logic Function Clock Buffer | ||
Input Signal Type LVPECL | ||
Number of Clock Inputs 2 | ||
Package Type SOIC | ||
Pin Count 8 | ||
The Renesas Electronics 853S011B is a low skew, high performance 1-to-2 Differential-to-2.5V/3.3V LVPECL/ECL Fanout Buffer. The 853S011B is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the 853S011B ideal for those clock distribution applications demanding well defined performance and repeatability.
Two differential 2.5V, 3.3V LVPECL/ECL outputs
One differential PCLK, nPCLK input pair
PCLK, nPCLK pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
Maximum output frequency: >2.5GHz
Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nPCLK input
Output skew: 5ps (typical)
Part-to-part skew: 130ps (maximum)
Propagation delay: 355ps (maximum)
One differential PCLK, nPCLK input pair
PCLK, nPCLK pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
Maximum output frequency: >2.5GHz
Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nPCLK input
Output skew: 5ps (typical)
Part-to-part skew: 130ps (maximum)
Propagation delay: 355ps (maximum)
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