Renesas Electronics 9DB106BGLF Clock Buffer 28-Pin TSSOP
- RS-stocknr.:
- 263-7981
- Fabrikantnummer:
- 9DB106BGLF
- Fabrikant:
- Renesas Electronics
Bulkkorting beschikbaar
Subtotaal (1 verpakking van 2 eenheden)*
€ 8,88
(excl. BTW)
€ 10,74
(incl. BTW)
GRATIS bezorging voor bestellingen vanaf € 90,00
Op voorraad
- Plus verzending 80 stuk(s) vanaf 15 april 2026
Heeft u meer nodig? Klik op 'Controleer leverdata' voor extra voorraad en levertijden.
Aantal stuks | Per stuk | Per verpakking* |
|---|---|---|
| 2 - 8 | € 4,44 | € 8,88 |
| 10 - 18 | € 3,975 | € 7,95 |
| 20 - 48 | € 3,895 | € 7,79 |
| 50 - 98 | € 3,765 | € 7,53 |
| 100 + | € 3,265 | € 6,53 |
*prijsindicatie
- RS-stocknr.:
- 263-7981
- Fabrikantnummer:
- 9DB106BGLF
- Fabrikant:
- Renesas Electronics
Specificaties
Datasheets
Wetgeving en conformiteit
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Maximum Input Frequency | 105MHz | |
| Maximum Propagation Delay Time | 150ps | |
| Mount Type | Surface | |
| Package Type | TSSOP | |
| Pin Count | 28 | |
| Minimum Supply Voltage | 2.7V | |
| Maximum Supply Voltage | 4.6V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Standards/Approvals | RoHS | |
| Series | 9DB106 REV L | |
| Length | 9.7mm | |
| Height | 1mm | |
| Automotive Standard | No | |
| Alles selecteren | ||
|---|---|---|
Merk Renesas Electronics | ||
Product Type Clock Buffer | ||
Maximum Input Frequency 105MHz | ||
Maximum Propagation Delay Time 150ps | ||
Mount Type Surface | ||
Package Type TSSOP | ||
Pin Count 28 | ||
Minimum Supply Voltage 2.7V | ||
Maximum Supply Voltage 4.6V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Standards/Approvals RoHS | ||
Series 9DB106 REV L | ||
Length 9.7mm | ||
Height 1mm | ||
Automotive Standard No | ||
- Land van herkomst:
- TW
The Renesas Electronics zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. It is driven by a differential SRC output pair from an IDT main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without spread-spectrum clocking.
SMBus Interface
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50 ps
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