Renesas Electronics 5P49V60A000NLG2 Clock Generator 24-Pin VFQFPN
- RS-stocknr.:
- 250-3451
- Fabrikantnummer:
- 5P49V60A000NLG2
- Fabrikant:
- Renesas Electronics
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We weten niet of dit item nog op voorraad komt, RS is van plan dit binnenkort uit ons assortiment te halen.
- RS-stocknr.:
- 250-3451
- Fabrikantnummer:
- 5P49V60A000NLG2
- Fabrikant:
- Renesas Electronics
Specificaties
Datasheets
Wetgeving en conformiteit
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Renesas Electronics | |
| Number of Elements per Chip | 4 | |
| Maximum Supply Current | 42 mA | |
| Maximum Input Frequency | 40MHz | |
| Mounting Type | Surface Mount | |
| Package Type | VFQFPN | |
| Pin Count | 24 | |
| Alles selecteren | ||
|---|---|---|
Merk Renesas Electronics | ||
Number of Elements per Chip 4 | ||
Maximum Supply Current 42 mA | ||
Maximum Input Frequency 40MHz | ||
Mounting Type Surface Mount | ||
Package Type VFQFPN | ||
Pin Count 24 | ||
The Renesas Electronics programmable clock generator is intended for automotive applications. Configurations may be stored in on-chip One-Time Programmable (OTP) memory or changed using I2C interface. This is Renesas sixth generation of programmable clock technology (VersaClock 6E).The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. A glitch less manual switchover function allows one of the redundant clocks to be selected during normal operation. Two select pins allow up to four different configurations to be programmed and accessible using processor GPIOs or bootstrapping. The different selections may be used for different operating modes (full function, partial function, partial power-down), regional standards (US, Japan, Europe) or system production margin testing. The device may be configured to use one of two I2C addresses to allow multiple devices to be used in a system.
Flexible power rails available
High-performance with low phase noise PLL and less than 0.5ps RMS typical phase jitter on outputs
Four banks of internal OTP memory
In-system or factory programmable
2 select pins accessible with processor GPIOs or bootstrapping
I2C serial programming interface
0xD0 or 0xD4 I2C address options allows multiple devices configured in a same system
Reference LVCMOS output clock
Redundant clock inputs with manual switchover
Programmable output enable or power-down mode
4 x 4 mm 24-VFQFPN wet table flank package
AEC-Q100 qualified
-40° to +105°C (Grade 2) temperature operation
High-performance with low phase noise PLL and less than 0.5ps RMS typical phase jitter on outputs
Four banks of internal OTP memory
In-system or factory programmable
2 select pins accessible with processor GPIOs or bootstrapping
I2C serial programming interface
0xD0 or 0xD4 I2C address options allows multiple devices configured in a same system
Reference LVCMOS output clock
Redundant clock inputs with manual switchover
Programmable output enable or power-down mode
4 x 4 mm 24-VFQFPN wet table flank package
AEC-Q100 qualified
-40° to +105°C (Grade 2) temperature operation
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