Nexperia 74HCT373D,652 D Type Latch, 8-Bit Non-Inverting, 20-Pin SO
- RS-stocknr.:
- 170-8071
- Fabrikantnummer:
- 74HCT373D,652
- Fabrikant:
- Nexperia
Informatie over voorraden is momenteel niet toegankelijk
- RS-stocknr.:
- 170-8071
- Fabrikantnummer:
- 74HCT373D,652
- Fabrikant:
- Nexperia
Specificaties
Datasheets
Wetgeving en conformiteit
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Nexperia | |
| Product Type | D Type Latch | |
| Logic Family | 74HCT | |
| Logic Function | D Type | |
| Number of Channels | 8 | |
| Polarity | Non-Inverting | |
| Mount Type | Surface | |
| Package Type | SO | |
| Pin Count | 20 | |
| Minimum Supply Voltage | 4.5V | |
| Maximum Supply Voltage | 5.5V | |
| Input Level | TTL | |
| Maximum Propagation Delay Time @ CL | 45ns | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 125°C | |
| Series | 74HCT | |
| Standards/Approvals | No | |
| Length | 13mm | |
| Height | 2.45mm | |
| Automotive Standard | No | |
| Output Type | 3 State | |
| Alles selecteren | ||
|---|---|---|
Merk Nexperia | ||
Product Type D Type Latch | ||
Logic Family 74HCT | ||
Logic Function D Type | ||
Number of Channels 8 | ||
Polarity Non-Inverting | ||
Mount Type Surface | ||
Package Type SO | ||
Pin Count 20 | ||
Minimum Supply Voltage 4.5V | ||
Maximum Supply Voltage 5.5V | ||
Input Level TTL | ||
Maximum Propagation Delay Time @ CL 45ns | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 125°C | ||
Series 74HCT | ||
Standards/Approvals No | ||
Length 13mm | ||
Height 2.45mm | ||
Automotive Standard No | ||
Output Type 3 State | ||
The 74HC373, 74HCT373 is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE.
Mixed 5 V and 3.3 V applications
Save board space
Low cost interface solutions
Improved signal integrity for complex layouts
Wide supply voltage range
Low propagation delay
Overvoltage tolerant
Source termination
Low input threshold
CMOS low power
Key applications
Memory controllers
Backplane interfaces
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