Infineon SRAM, CY7C1041G-10ZSXI- 4 MB
- RS-stocknr.:
- 273-7349
- Fabrikantnummer:
- CY7C1041G-10ZSXI
- Fabrikant:
- Infineon
Subtotaal (1 tray van 135 eenheden)*
€ 534,60
(excl. BTW)
€ 646,65
(incl. BTW)
Voeg 135 eenheden toe voor gratis bezorging
Tijdelijk niet op voorraad
- Verzending vanaf 15 juni 2026
Heeft u meer nodig? Klik op 'Controleer leverdata' voor extra voorraad en levertijden.
Aantal stuks | Per stuk | Per tray* |
|---|---|---|
| 135 + | € 3,96 | € 534,60 |
*prijsindicatie
- RS-stocknr.:
- 273-7349
- Fabrikantnummer:
- CY7C1041G-10ZSXI
- Fabrikant:
- Infineon
Specificaties
Datasheets
Wetgeving en conformiteit
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Infineon | |
| Memory Size | 4MB | |
| Product Type | SRAM | |
| Organisation | 256 K x 16 | |
| Number of Words | 256K | |
| Number of Bits per Word | 16 | |
| Minimum Supply Voltage | 0.5V | |
| Mount Type | Surface | |
| Maximum Supply Voltage | 0.5V | |
| Minimum Operating Temperature | -40°C | |
| Package Type | TSOP II | |
| Maximum Operating Temperature | 85°C | |
| Pin Count | 44 | |
| Length | 18.51mm | |
| Standards/Approvals | RoHS | |
| Width | 1.19 mm | |
| Series | CY7C1041G | |
| Height | 10.26mm | |
| Supply Current | 45mA | |
| Alles selecteren | ||
|---|---|---|
Merk Infineon | ||
Memory Size 4MB | ||
Product Type SRAM | ||
Organisation 256 K x 16 | ||
Number of Words 256K | ||
Number of Bits per Word 16 | ||
Minimum Supply Voltage 0.5V | ||
Mount Type Surface | ||
Maximum Supply Voltage 0.5V | ||
Minimum Operating Temperature -40°C | ||
Package Type TSOP II | ||
Maximum Operating Temperature 85°C | ||
Pin Count 44 | ||
Length 18.51mm | ||
Standards/Approvals RoHS | ||
Width 1.19 mm | ||
Series CY7C1041G | ||
Height 10.26mm | ||
Supply Current 45mA | ||
The Infineon Static RAM are high performance CMOS fast static RAM device with embedded ECC. This Static RAM device offered in single chip enable option and in multiple pin configurations. This device includes an ERR pin that signals an error detection and correction event during a read cycle. Data writes are performed by asserting the chip enable and write enable inputs LOW, while providing the data on IO 0 through IO 15 and address on A0 through A17 pins. The byte high enable and byte low enable inputs control write operations to the upper and lower bytes of the specified memory location.
High speed
Low active and standby currents
1 bit error detection and correction
TTL compatible inputs and outputs
Embedded ECC for single bit error correction