Winbond W972GG6KB25I, SDRAM 2Gbit Surface Mount, 800MHz, 1.7 V to 1.9 V, 84-Pin WBGA
- RS-stocknr.:
- 188-2835P
- Fabrikantnummer:
- W972GG6KB25I
- Fabrikant:
- Winbond
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We weten niet of dit item nog op voorraad komt, RS is van plan dit binnenkort uit ons assortiment te halen.
- RS-stocknr.:
- 188-2835P
- Fabrikantnummer:
- W972GG6KB25I
- Fabrikant:
- Winbond
Specificaties
Datasheets
Wetgeving en conformiteit
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Winbond | |
| Memory Size | 2Gbit | |
| SDRAM Class | DDR2 | |
| Organisation | 256M x 8 bit | |
| Data Rate | 800MHz | |
| Data Bus Width | 16bit | |
| Address Bus Width | 17bit | |
| Number of Bits per Word | 8bit | |
| Maximum Random Access Time | 0.4ns | |
| Number of Words | 256M | |
| Mounting Type | Surface Mount | |
| Package Type | WBGA | |
| Pin Count | 84 | |
| Dimensions | 12.6 x 8.1 x 0.6mm | |
| Height | 0.6mm | |
| Length | 12.6mm | |
| Width | 8.1mm | |
| Minimum Operating Temperature | -40 °C | |
| Minimum Operating Supply Voltage | 1.7 V | |
| Maximum Operating Temperature | +95 °C | |
| Maximum Operating Supply Voltage | 1.9 V | |
| Alles selecteren | ||
|---|---|---|
Merk Winbond | ||
Memory Size 2Gbit | ||
SDRAM Class DDR2 | ||
Organisation 256M x 8 bit | ||
Data Rate 800MHz | ||
Data Bus Width 16bit | ||
Address Bus Width 17bit | ||
Number of Bits per Word 8bit | ||
Maximum Random Access Time 0.4ns | ||
Number of Words 256M | ||
Mounting Type Surface Mount | ||
Package Type WBGA | ||
Pin Count 84 | ||
Dimensions 12.6 x 8.1 x 0.6mm | ||
Height 0.6mm | ||
Length 12.6mm | ||
Width 8.1mm | ||
Minimum Operating Temperature -40 °C | ||
Minimum Operating Supply Voltage 1.7 V | ||
Maximum Operating Temperature +95 °C | ||
Maximum Operating Supply Voltage 1.9 V | ||
- Land van herkomst:
- TW
The W972GG6KB is a 2G bits DDR2 SDRAM, and speed involving -18, -25/25I, and -3/-3I.
Double Data Rate architecture: two data transfers per clock cycle
CAS Latency: 3, 4, 5, 6 and 7
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and /DQS ) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and /CLK)
Data masks (DM) for write data
Commands entered on each positive CLK edge, data and data mask are referenced to both edges of /DQS
Posted /CAS programmable additive latency supported to make command and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18
CAS Latency: 3, 4, 5, 6 and 7
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and /DQS ) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and /CLK)
Data masks (DM) for write data
Commands entered on each positive CLK edge, data and data mask are referenced to both edges of /DQS
Posted /CAS programmable additive latency supported to make command and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18