Alliance Memory AS4C1G8D4A-62BIN, SDRAM 1GBit Surface Mount, 78-Pin FBGA
- RS-stocknr.:
- 665-384
- Fabrikantnummer:
- AS4C1G8D4A-62BIN
- Fabrikant:
- Alliance Memory
Subtotaal (1 eenheid)*
€ 22,63
(excl. BTW)
€ 27,38
(incl. BTW)
GRATIS bezorging voor bestellingen vanaf € 75,00
Op voorraad
- 209 stuk(s) klaar voor verzending vanaf een andere locatie
Heeft u meer nodig? Klik op 'Controleer leverdata' voor extra voorraad en levertijden.
Aantal stuks | Per stuk |
|---|---|
| 1 + | € 22,63 |
*prijsindicatie
- RS-stocknr.:
- 665-384
- Fabrikantnummer:
- AS4C1G8D4A-62BIN
- Fabrikant:
- Alliance Memory
Specificaties
Datasheets
Wetgeving en conformiteit
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Alliance Memory | |
| Memory Size | 1GBit | |
| SDRAM Class | DDR4 | |
| Organisation | 1G x 8 | |
| Data Bus Width | 8bit | |
| Mounting Type | Surface Mount | |
| Package Type | FBGA | |
| Pin Count | 78 | |
| Alles selecteren | ||
|---|---|---|
Merk Alliance Memory | ||
Memory Size 1GBit | ||
SDRAM Class DDR4 | ||
Organisation 1G x 8 | ||
Data Bus Width 8bit | ||
Mounting Type Surface Mount | ||
Package Type FBGA | ||
Pin Count 78 | ||
- Land van herkomst:
- TW
The Alliance Memory 8Gb DDR4 DRAM in a 78-ball FBGA package supports JEDEC clock jitter specifications and features a bidirectional differential data strobe along with differential clocks. It is internally organized into 16 banks, grouped as four sets of four banks each, with separated I/O gating structures by bank group. The device uses an 8n-bit prefect architecture and supports power-saving features such as precharge and active power-down, auto refresh, self refresh, low-power auto self refresh (LPASR), self refresh abort, and fine granularity refresh, ensuring efficient and high-performance operation.
Internal VREFDQ Training
Read Preamble Training
Control Gear Down Mode
Per DRAM Addressability
Output Driver Impedance Control
Dynamic on-die termination
Read Preamble Training
Control Gear Down Mode
Per DRAM Addressability
Output Driver Impedance Control
Dynamic on-die termination
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