Alliance Memory AS4C256M8D3LC-12BINTR SDRAM 2 GB Surface, 78-Pin 8 bit FBGA-78 Ball
- RS-stocknr.:
- 425-286
- Fabrikantnummer:
- AS4C256M8D3LC-12BINTR
- Fabrikant:
- Alliance Memory
Subtotaal (1 rol van 2500 eenheden)*
€ 20.812,50
(excl. BTW)
€ 25.182,50
(incl. BTW)
Informatie over voorraden is momenteel niet toegankelijk - Controleer het later nog eens opnieuw
Aantal stuks | Per stuk | Per rol* |
|---|---|---|
| 2500 + | € 8,325 | € 20.812,50 |
*prijsindicatie
- RS-stocknr.:
- 425-286
- Fabrikantnummer:
- AS4C256M8D3LC-12BINTR
- Fabrikant:
- Alliance Memory
Specificaties
Datasheets
Wetgeving en conformiteit
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Alliance Memory | |
| Memory Size | 2GB | |
| Product Type | SDRAM | |
| Data Bus Width | 8bit | |
| Maximum Clock Frequency | 800MHz | |
| Number of Bits per Word | 8 | |
| Maximum Random Access Time | 20ns | |
| Mount Type | Surface | |
| Package Type | FBGA-78 Ball | |
| Pin Count | 78 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 95°C | |
| Series | AS4C256M8D3LC | |
| Standards/Approvals | JEDEC, RoHS | |
| Length | 10.5mm | |
| Height | 1mm | |
| Maximum Supply Voltage | 1.35V | |
| Automotive Standard | No | |
| Minimum Supply Voltage | 1.283V | |
| Alles selecteren | ||
|---|---|---|
Merk Alliance Memory | ||
Memory Size 2GB | ||
Product Type SDRAM | ||
Data Bus Width 8bit | ||
Maximum Clock Frequency 800MHz | ||
Number of Bits per Word 8 | ||
Maximum Random Access Time 20ns | ||
Mount Type Surface | ||
Package Type FBGA-78 Ball | ||
Pin Count 78 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 95°C | ||
Series AS4C256M8D3LC | ||
Standards/Approvals JEDEC, RoHS | ||
Length 10.5mm | ||
Height 1mm | ||
Maximum Supply Voltage 1.35V | ||
Automotive Standard No | ||
Minimum Supply Voltage 1.283V | ||
- Land van herkomst:
- TW
The Alliance Memory 2gb Double-Data-Rate-3 (DDR3L) DRAMs is double data rate architecture to achieve high-speed operation. The chip is designed to comply with all key DDR3L DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Write Leveling
ZQ Calibration
RoHS compliant
Auto Refresh and Self Refresh
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