STMicroelectronics STM32MP233DAJ3 ARM Cortex A35, ARM Cortex M33 Microprocessor STM32MP23xA/D 16 bit ARM V8-M, 64 Bit,
- RS-stocknr.:
- 482-989
- Fabrikantnummer:
- STM32MP233DAJ3
- Fabrikant:
- STMicroelectronics
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- RS-stocknr.:
- 482-989
- Fabrikantnummer:
- STM32MP233DAJ3
- Fabrikant:
- STMicroelectronics
Specificaties
Datasheets
Wetgeving en conformiteit
Productomschrijving
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Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | STMicroelectronics | |
| Series | STM32MP23xA/D | |
| Product Type | Microprocessor | |
| Device Core | ARM Cortex A35, ARM Cortex M33 | |
| Data Bus Width | 16bit | |
| Instruction Set Architecture | ARM V8-M, 64 Bit, Arm Cortex | |
| Maximum Clock Frequency | 1.5GHz | |
| Interface Type | USB 2.0, UART, SDM, USART, SPI, CAN, I3C, CSI, DDR4, LPDDR4, FMC, Parallel, I2C, NAND, DDR3L, DSI, LVDS, Ethernet, MIPI | |
| Package Type | TFBGA361 | |
| Minimum Supply Voltage | 1.71V | |
| Pin Count | 361 | |
| Maximum Supply Voltage | 3.6V | |
| Standards/Approvals | JEDEC, ECOPACK2 | |
| Number of Cores | 2 | |
| Automotive Standard | No | |
| Alles selecteren | ||
|---|---|---|
Merk STMicroelectronics | ||
Series STM32MP23xA/D | ||
Product Type Microprocessor | ||
Device Core ARM Cortex A35, ARM Cortex M33 | ||
Data Bus Width 16bit | ||
Instruction Set Architecture ARM V8-M, 64 Bit, Arm Cortex | ||
Maximum Clock Frequency 1.5GHz | ||
Interface Type USB 2.0, UART, SDM, USART, SPI, CAN, I3C, CSI, DDR4, LPDDR4, FMC, Parallel, I2C, NAND, DDR3L, DSI, LVDS, Ethernet, MIPI | ||
Package Type TFBGA361 | ||
Minimum Supply Voltage 1.71V | ||
Pin Count 361 | ||
Maximum Supply Voltage 3.6V | ||
Standards/Approvals JEDEC, ECOPACK2 | ||
Number of Cores 2 | ||
Automotive Standard No | ||
- Land van herkomst:
- TW
The STMicroelectronics MPU with Dual Arm Cortex-A35 devices are based on the high-performance single or dual-core Arm Cortex-A35 64-bit RISC core operating at up to 1.5 GHz. The Cortex‑A35 processor includes a 32-Kbyte L1 instruction cache for each CPU, a 32-Kbyte L1 data cache for each CPU, and a 512-Kbyte L2 cache. The Cortex‑A35 processor uses a highly efficient 8-stage in-order pipeline that has been extensively optimized to provide full Armv8-A features while maximizing area and power efficiency.
Internal temperature sensors
Low power consumption
Clock management
Digital parallel interface up to 16 bit input or output
Two Octo-SPI memory interfaces
DDR memory retention in Standby mode
Controls for PMIC companion chip
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