STMicroelectronics STM32MP231CAJ3 ARM Cortex A35, ARM Cortex M33 Microprocessor STM32MP23xC/F 16 bit ARM V8-A, Arm
- RS-stocknr.:
- 482-981
- Fabrikantnummer:
- STM32MP231CAJ3
- Fabrikant:
- STMicroelectronics
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- RS-stocknr.:
- 482-981
- Fabrikantnummer:
- STM32MP231CAJ3
- Fabrikant:
- STMicroelectronics
Specificaties
Datasheets
Wetgeving en conformiteit
Productomschrijving
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Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | STMicroelectronics | |
| Product Type | Microprocessor | |
| Series | STM32MP23xC/F | |
| Device Core | ARM Cortex A35, ARM Cortex M33 | |
| Data Bus Width | 16bit | |
| Instruction Set Architecture | ARM V8-A, Arm Cortex, ARM V8-M | |
| Maximum Clock Frequency | 1.5GHz | |
| Interface Type | LPUART, LVDS, I2C, NAND, Parallel RGB, PSSI, Ethernet, FMC Parallel, DSI, CAN FD, DDR4, LPDDR4, LCD, I3C, DCMI, DCMIPP, DDR3L, SPDIF RX, USART, SAI, USB 2.0, SPI, SDM, UART | |
| Minimum Supply Voltage | 1.71V | |
| Package Type | TFBGA361 | |
| Maximum Supply Voltage | 3.6V | |
| Pin Count | 361 | |
| Standards/Approvals | ECOPACK2 | |
| Automotive Standard | No | |
| Number of Cores | 2 | |
| Alles selecteren | ||
|---|---|---|
Merk STMicroelectronics | ||
Product Type Microprocessor | ||
Series STM32MP23xC/F | ||
Device Core ARM Cortex A35, ARM Cortex M33 | ||
Data Bus Width 16bit | ||
Instruction Set Architecture ARM V8-A, Arm Cortex, ARM V8-M | ||
Maximum Clock Frequency 1.5GHz | ||
Interface Type LPUART, LVDS, I2C, NAND, Parallel RGB, PSSI, Ethernet, FMC Parallel, DSI, CAN FD, DDR4, LPDDR4, LCD, I3C, DCMI, DCMIPP, DDR3L, SPDIF RX, USART, SAI, USB 2.0, SPI, SDM, UART | ||
Minimum Supply Voltage 1.71V | ||
Package Type TFBGA361 | ||
Maximum Supply Voltage 3.6V | ||
Pin Count 361 | ||
Standards/Approvals ECOPACK2 | ||
Automotive Standard No | ||
Number of Cores 2 | ||
- Land van herkomst:
- TW
The STMicroelectronics MPU with Arm Cortex-A35 devices are based on the high performance single or dual-core Arm Cortex-A35 64-bit RISC core operating at up to 1.5 GHz. The Cortex‑A35 processor includes a 32-Kbyte L1 instruction cache for each CPU, a 32-Kbyte L1 data cache for each CPU, and a 512-Kbyte L2 cache. The Cortex‑A35 processor uses a highly efficient 8-stage in-order pipeline that has been extensively optimized to provide full Armv8-A features while maximizing area and power efficiency.
Low power consumption
Clock management
Digital parallel interface up to 16 bit input or output
Internal temperature sensors
Two Octo-SPI memory interfaces
Up to 39 communication peripherals
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