Microchip PIC, PIC18 Microcontroller MCU, 28-Pin SPDIP
- RS-stocknr.:
- 264-8068
- Fabrikantnummer:
- PIC18F25K83-I/SP
- Fabrikant:
- Microchip
Bulkkorting beschikbaar
Subtotaal (1 verpakking van 2 eenheden)*
€ 5,50
(excl. BTW)
€ 6,66
(incl. BTW)
GRATIS bezorging voor bestellingen vanaf € 75,00
Op voorraad
- Plus verzending 92 stuk(s) vanaf 08 december 2025
Heeft u meer nodig? Klik op 'Controleer leverdata' voor extra voorraad en levertijden.
Aantal stuks | Per stuk | Per verpakking* |
|---|---|---|
| 2 - 2 | € 2,75 | € 5,50 |
| 4 - 28 | € 2,70 | € 5,40 |
| 30 - 104 | € 2,525 | € 5,05 |
| 106 + | € 2,45 | € 4,90 |
*prijsindicatie
- RS-stocknr.:
- 264-8068
- Fabrikantnummer:
- PIC18F25K83-I/SP
- Fabrikant:
- Microchip
Specificaties
Datasheets
Wetgeving en conformiteit
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Microchip | |
| Family Name | PIC18 | |
| Package Type | SPDIP | |
| Mounting Type | Through Hole | |
| Pin Count | 28 | |
| Device Core | PIC | |
| Alles selecteren | ||
|---|---|---|
Merk Microchip | ||
Family Name PIC18 | ||
Package Type SPDIP | ||
Mounting Type Through Hole | ||
Pin Count 28 | ||
Device Core PIC | ||
The Microchip PIC series 8bit low power, high performance MCU with CAN technology that can be used in automotive and industrial applications. It has 32 KB flash memory, 2KB RAM and 28 pins. It's operating temperature ranges between -40°C to +85°C (Industrial).
Supports CAN 1.2, 2.0A and 2.0B
Six modes of operation
Supports legacy - Fully backward compatibly
Interrupt vector table
Programmable single or dual priority
Two level hardware context saving
Eliminates need for CPU involvement in data transfers
Access to all memory spaces and peripherals
Flexible source and destination message sizes
Programmable DMA priority
Six modes of operation
Supports legacy - Fully backward compatibly
Interrupt vector table
Programmable single or dual priority
Two level hardware context saving
Eliminates need for CPU involvement in data transfers
Access to all memory spaces and peripherals
Flexible source and destination message sizes
Programmable DMA priority
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