Toshiba 74HC132D, Quad 2-Input NAND Schmitt Trigger Logic Gate, 14-Pin SOIC
- RS-stocknr.:
- 171-3542P
- Fabrikantnummer:
- 74HC132D
- Fabrikant:
- Toshiba
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- RS-stocknr.:
- 171-3542P
- Fabrikantnummer:
- 74HC132D
- Fabrikant:
- Toshiba
Specificaties
Datasheets
Wetgeving en conformiteit
Productomschrijving
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Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Toshiba | |
| Logic Function | NAND | |
| Mounting Type | Surface Mount | |
| Number of Elements | 4 | |
| Number of Inputs per Gate | 2 | |
| Schmitt Trigger Input | Yes | |
| Package Type | SOIC | |
| Pin Count | 14 | |
| Logic Family | 74HC | |
| Input Type | CMOS, Schmitt Trigger | |
| Maximum Operating Supply Voltage | 6 V | |
| Maximum High Level Output Current | -5.2mA | |
| Maximum Propagation Delay Time @ Maximum CL | 140 ns @ 50 pF | |
| Minimum Operating Supply Voltage | 2 V | |
| Maximum Low Level Output Current | 5.2mA | |
| Output Type | CMOS, LSTTL | |
| Dimensions | 8.95 x 3.9 x 1.38mm | |
| Minimum Operating Temperature | -40 °C | |
| Width | 3.9mm | |
| Height | 1.38mm | |
| Length | 8.95mm | |
| Propagation Delay Test Condition | 50pF | |
| Maximum Operating Temperature | +85 °C | |
| Alles selecteren | ||
|---|---|---|
Merk Toshiba | ||
Logic Function NAND | ||
Mounting Type Surface Mount | ||
Number of Elements 4 | ||
Number of Inputs per Gate 2 | ||
Schmitt Trigger Input Yes | ||
Package Type SOIC | ||
Pin Count 14 | ||
Logic Family 74HC | ||
Input Type CMOS, Schmitt Trigger | ||
Maximum Operating Supply Voltage 6 V | ||
Maximum High Level Output Current -5.2mA | ||
Maximum Propagation Delay Time @ Maximum CL 140 ns @ 50 pF | ||
Minimum Operating Supply Voltage 2 V | ||
Maximum Low Level Output Current 5.2mA | ||
Output Type CMOS, LSTTL | ||
Dimensions 8.95 x 3.9 x 1.38mm | ||
Minimum Operating Temperature -40 °C | ||
Width 3.9mm | ||
Height 1.38mm | ||
Length 8.95mm | ||
Propagation Delay Test Condition 50pF | ||
Maximum Operating Temperature +85 °C | ||
The 74HC132D is a high speed CMOS 2-INPUT NAND SCHMITT TRIGGER GATE fabricated with silicon gateC2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. Pin configuration and function are the same as the 74HC00D but the inputs have 25% VCC hysteresis and with its schmitt trigger inputs, the 74HC132D can be used as a line receiver for slow input signals. All inputs are equipped with protection circuits against static discharge or transient excess voltage.
High speed: tpd = 11 ns (typ.) at VCC = 5 V
Low power dissipation: ICC = 1.0 μA (max) at Ta = 25
High noise immunity: VH = 1.1 V (typ.) at VCC = 4.5 V
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 to 6.0 V
Low power dissipation: ICC = 1.0 μA (max) at Ta = 25
High noise immunity: VH = 1.1 V (typ.) at VCC = 4.5 V
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 to 6.0 V