Toshiba 74HC21D, 2 4-Input AND Logic Gate, 14-Pin SOIC
- RS-stocknr.:
- 171-3385
- Fabrikantnummer:
- 74HC21D
- Fabrikant:
- Toshiba
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We weten niet of dit item nog op voorraad komt, RS is van plan dit binnenkort uit ons assortiment te halen.
- RS-stocknr.:
- 171-3385
- Fabrikantnummer:
- 74HC21D
- Fabrikant:
- Toshiba
Specificaties
Datasheets
Wetgeving en conformiteit
Productomschrijving
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Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Toshiba | |
| Number of Elements | 2 | |
| Number of Inputs per Gate | 4 | |
| Logic Function | AND | |
| Schmitt Trigger Input | No | |
| Product Type | Logic Gate | |
| Pin Count | 14 | |
| Package Type | SOIC | |
| Automotive Standard | No | |
| Height | 1.38 mm | |
| Input Type | CMOS | |
| Length | 8.95 mm | |
| Logic Family | 74HC | |
| Maximum High Level Output Current | -5.2 mA | |
| Maximum Low Level Output Current | 5.2 mA | |
| Maximum Operating Temperature | 85 °C | |
| Maximum Propagation Delay Time @ CL | 25 ns | |
| Maximum Supply Voltage | 6 V | |
| Minimum Operating Temperature | -40 °C | |
| Minimum Supply Voltage | 2 V | |
| Mount Type | Surface | |
| Output Type | Buffer, CMOS | |
| Series | 74HC | |
| Standards/Approvals | No | |
| Width | 3.9 mm | |
| Alles selecteren | ||
|---|---|---|
Merk Toshiba | ||
Number of Elements 2 | ||
Number of Inputs per Gate 4 | ||
Logic Function AND | ||
Schmitt Trigger Input No | ||
Product Type Logic Gate | ||
Pin Count 14 | ||
Package Type SOIC | ||
Automotive Standard No | ||
Height 1.38 mm | ||
Input Type CMOS | ||
Length 8.95 mm | ||
Logic Family 74HC | ||
Maximum High Level Output Current -5.2 mA | ||
Maximum Low Level Output Current 5.2 mA | ||
Maximum Operating Temperature 85 °C | ||
Maximum Propagation Delay Time @ CL 25 ns | ||
Maximum Supply Voltage 6 V | ||
Minimum Operating Temperature -40 °C | ||
Minimum Supply Voltage 2 V | ||
Mount Type Surface | ||
Output Type Buffer, CMOS | ||
Series 74HC | ||
Standards/Approvals No | ||
Width 3.9 mm | ||
The 74HC21D is a high speed CMOS 4-INPUT AND GATE fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The internal circuit is composed of 4 stages including buffer an output, which provide high noise immunity and stable output. All inputs are equipped with protection circuits against static discharge or transient excess voltage
High speed: tpd = 10 ns (typ.) at VCC = 5 V
Low power dissipation: ICC = 1.0 μA (max) Ta = 25
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 to 6.0 V
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