Infineon NOR 16Mbit CFI Flash Memory 48-Pin TSOP, S29AL016J70TFI023

Subtotaal (1 verpakking van 5 eenheden)*

€ 11,52

(excl. BTW)

€ 13,94

(incl. BTW)

Add to Basket
selecteer of typ hoeveelheid
Op voorraad
  • 1.895 stuk(s) klaar voor verzending vanaf een andere locatie
Heeft u meer nodig? Klik op 'Controleer leverdata' voor extra voorraad en levertijden.
Aantal stuks
Per stuk
Per verpakking*
5 +€ 2,304€ 11,52

*prijsindicatie

Verpakkingsopties
RS-stocknr.:
193-8789
Fabrikantnummer:
S29AL016J70TFI023
Fabrikant:
Infineon
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren

Merk

Infineon

Memory Size

16Mbit

Interface Type

CFI

Package Type

TSOP

Pin Count

48

Organisation

2M x 8 bit

Mounting Type

Surface Mount

Cell Type

NOR

Minimum Operating Supply Voltage

2.7 V

Maximum Operating Supply Voltage

3.6 V

Block Organisation

Asymmetrical

Length

12mm

Height

1.05mm

Width

18.4mm

Dimensions

18.4 x 12 x 1.05mm

Maximum Random Access Time

70ns

Number of Bits per Word

8bit

Maximum Operating Temperature

+85 °C

Automotive Standard

AEC-Q100

Series

S29AL

Number of Words

2M

Minimum Operating Temperature

-40 °C

Land van herkomst:
TH
The S29AL016J is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2,097,152 bytes or 1,048,576 words. The device is offered in 48-ball Fine-pitch BGA (0.8 mm pitch), 64-ball Fortified BGA (1.0 mm pitch) and 48pin TSOP packages. The word-wide data (x16)appears on DQ15–DQ0, the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in-system with the standard system 3.0 volt VCC supply. A 12.0 V VPP or 5.0 VCC are not required for write or erase operations. The device can also be programmed in standard EPROM programmers.
The device offers access time of 55 ns allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7(Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.

Gerelateerde Links