DSPIC33FJ256MC710-I/PF Microchip DSPIC33FJ256MC710, 16bit Digital Signal Processor 80MHz 256 kB Flash 100-Pin TQFP

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€ 795,60

(excl. BTW)

€ 963,00

(incl. BTW)

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  • Verzending vanaf 14 januari 2026
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RS-stocknr.:
177-3518
Fabrikantnummer:
DSPIC33FJ256MC710-I/PF
Fabrikant:
Microchip
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Merk

Microchip

Maximum Frequency

80MHz

Series

DSPIC33FJ256MC710

Device Million Instructions per Second

40MIPS

Data Bus Width

16bit

RAM Size

30 kB

Instruction Set Architecture

Harvard

Program Memory Size

256 kB

Program Memory Type

Flash

Numeric and Arithmetic Format

ALU

Mounting Type

Surface Mount

Package Type

TQFP

Pin Count

100

Number of UART Channels

2

Timer Resolution

16 bit, 32bit

Height

1.05mm

PWM Channels

8

Width

12mm

Number of Timers

2

Number of I2C Channels

2

ADCs

2 (24 x 12 bit)

Length

12mm

Number of PWM Units

1

Maximum Operating Temperature

+85 °C

Number of SPI Channels

2

Pulse Width Modulation

1 (8 x 16 bit)

Dimensions

12 x 12 x 1.05mm

Timers

4 x 32-bit, 9 x 16-bit

Number of ADC Units

2

ADC Channels

24

Number of CAN Channels

2

PWM Resolution

16bit

Minimum Operating Temperature

-40 °C

ADC Resolution

12bit

dsPIC33F Motor Control Digital Signal Controller (DSC) with seamless migration options to PIC24 MCUs and dsPIC30F DSCs in similar packages.

DC–40 MIPS (40 MIPS @ 3.0-3.6V, -40°C - +85°C)
Industrial temperature range (-40°C - +85°C)
Modified Harvard architecture
16-bit wide data path
24-bit wide instructions
Linear program memory to 4M instruction words
Linear data memory to 64Kb
83 base instructions
16 16-bit General Purpose Registers
2 40-bit accumulators:With rounding, saturation options
Flexible, powerful addressing modes:Indirect, Modulo, Bit-Reversed
16 x 16 fractional/integer multiply operations
32/16 and 16/16 divide operations
Single-cycle multiply and accumulate:- Accumulator write back for DSP operations Dual data fetch
Up to ±16-bit shifts for up to 40-bit dataDirect Memory Access (DMA)
8-channel hardware DMA
2Kb dual ported DMA buffer area (DMA RAM) to store data transferred via DMA
Most peripherals support DMAInterrupt Controller
5-cycle latency

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