Infineon Clock Generator, 16-Pin 6 TSSOP

The Infineon Clock Generator has three PLLs which, when combined with the reference, allow up to four independent frequencies to be output on up to six pins. These three PLLs are completely programmable. The PLL1 generates a frequency that is equal to the reference divided by an 8 bit divider and multiplied by an 11 bit divider in the PLL feedback loop. The frequency select through three external LVTTL inputs.

Ultra wide divide counters